Senior Engineer RTL Design
Senior Engineer RTL Design
Arrow Electronics5-7 Years
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Position
Senior Engineer RTL Design
Job Description
Principal Accountabilities
Typically requires 5–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.
Location:
IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)
Time Type
Full time
Job Category
Engineering Services
Senior Engineer RTL Design
Job Description
Principal Accountabilities
- RTL development for ASIC / FPGA
- Responsible for completion of front end design flow (spec to RTL / Netlist)
- Design, micro architect & do RTL coding, Lint, CDC
- Support existing sustenance designs
- Collaborate with Hardware board design engineers for system level designs, Board level block diagram design and validation of hardware, utilizing the Company specified hardware design tools
- Requires in-depth knowledge and experience
- Solves complex problems; takes a new perspective using existing solutions
- Works independently; receives minimal guidance
- Acts as a resource for colleagues with less experience
- Represents the level at which career may stabilize for many years or even until retirement
- Contributes to process improvements
- Typically resolves problems using existing solutions
- Provides informal guidance to junior staff
- Works with minimal guidance
Typically requires 5–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.
Location:
IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)
Time Type
Full time
Job Category
Engineering Services
More Info
Key Skills
About Company
Skills:
Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog
Skills:
Verilog, Synthesis, ECO fixes, asynchronous interfaces, Timing Concepts, formal verification, SoC design and integration, multi-clock designs, SoC clocking reset architecture, System-Verilog, Logic design RTL coding
Skills:
Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc
Skills:
telemetry , Verilog, System Verilog, Debug, secure MMIO access-control, AXI-Lite, transaction error handling, Axi, APB, EDA Tools, parity ECC schemes, RTL Coding, privilege-based filtering, firewall logic, RAS concepts