RTL Design Engineer ( Lead / Senior )

Job Description:

Experience Level: 6 - 12 Years

Location: Bangalore / Hyderabad

Role: Senior / Lead

Work Mode: Work from office ( 5 days a week )

Required Skills

• Experience in Logic design / RTL coding is a must.
• Experience in SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in multi-clock designs and asynchronous interfaces is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communication skills.
• Proactive, creative, curious, motivated to learn and contribute, with good collaboration skills