C
Sr Principal Design Engineer
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Sr Principal Design Engineer
Cadence Design Systems (India) Pvt LtdEarly Applicant
- Posted 3 months ago
- Be among the first 10 applicants
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
We're doing work that matters. Help us solve what others can't.
More Info
Key Skills
SV
SDF sim debug
test-bench development
functional and code coverages
closure constraint randomization
assertions development
eRM methodology
About Company
Skills:
static timing analysis, PCIe protocol stack, MSI interrupt handling, Simulation Tools, CDC design principles, systemverilog, asynchronous FIFO implementation, RTL design using Verilog, DMA engines, PXC interfaces, Synthesis, linting, formal verification, waveform debugging, assertion-based design methodologies
Skills:
System Verilog, Pcie, Uvm, PXC, CXL, RTL Design using Verilog