Design Verification
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI,
Minimum Qualifications:
- Experience Level:
- Education Requirements:
- Develop and signoff on test plans and test cases
- Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture
- strong knowledge of Verilog, System Verilog, UVM, C/C++
- Experience in usage of assertions, constrained random generation, functional/code coverage
- Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows
- Analytical debugging skills
- Knowledge on C Based Testcases
- Knowledge of SoC,Memory and Cache Architectures
- Preferred Qualifications:
- Knowledge of high-speed interfaces like Quad/Octa-SPI
- Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN
- Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee
- Mentoring skills
- Exceptional problem-solving skills
- Good written and oral communication skills
More Info
About Company
Skills:
SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog
Skills:
Gate Level Simulations, subsystem SoC verification, real number modeling, regression management, Vplan execution, Uvm, systemverilog
Skills:
simvision , python, perl, SV-UVM, Verdi, Verisium, Xcellium, Digital Simulation Tools, virtuoso
Skills:
Verilog, Ethernet, System Verilog, coverage closure techniques, Flex Ethernet, Otn, Uvm, regression management flows, formal verification, assertion-based test, self-checking testbenches, Interlaken
Skills:
C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification