SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog

simvision , python, perl, SV-UVM, Verdi, Verisium, Xcellium, Digital Simulation Tools, virtuoso

Verilog, Ethernet, System Verilog, coverage closure techniques, Flex Ethernet, Otn, Uvm, regression management flows, formal verification, assertion-based test, self-checking testbenches, Interlaken

Gate Level Simulations, subsystem SoC verification, real number modeling, regression management, Vplan execution, Uvm, systemverilog

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Uvm, testbench architecture, regression management, debug methodologies, verification methodology automation, AI-assisted workflows, verification planning, assertions, verification metrics, systemverilog, functional coverage, constrained-random verification

Coverage models, Uvm, CPU Core Verification, Constrained-random tests, systemverilog, Architecture Validation, Testbenches, Checkers, Scoreboards