Design Verification Engineer
- Posted 2 months ago
- Be among the first 30 applicants
Job Description
We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level.
Skills:
- Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM.
- Generic knowhow on Digital Design and Verification methodologies.
- Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
- Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
- Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator).
- Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
- Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
Traits:
- Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
- Solutions orientation; Quality driven; Execution minded
More Info
Key Skills
About Company
Skills:
SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog
Skills:
Gate Level Simulations, subsystem SoC verification, real number modeling, regression management, Vplan execution, Uvm, systemverilog
Skills:
C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog
Skills:
Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools
Skills:
Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm