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Showing 6 jobs
Skills:
SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog
Skills:
Gate Level Simulations, subsystem SoC verification, real number modeling, regression management, Vplan execution, Uvm, systemverilog
Skills:
C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog
Skills:
Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools
Skills:
Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm
Skills:
Vcs, System Verilog, Xcelium, Verdi, DVE, Questa, Uvm, SVA assertions
