Analog layout Engineer

FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

matching , shielding , Dac, Routing, GXL, Cadence Virtuoso Layout XL, LVS, Bandgap, PEX, EMIR verification, floorplanning, ADC, advanced technology nodes, Op-Amp, LDO, ERC, Placement, DRC, Analog Mixed-Signal Layout Design, SERDES, Pll

Dac, Full Custom Analog Layout, Analog Mixed-Signal Layout, RF Layout, Pll, LNA, mixers, VCO, ADC, Cadence Virtuoso XL, Cadence Virtuoso GXL, Calibre, DRC, LVS, ERC, Antenna Checks, Device Matching, Symmetry, Common Centroid, Interdigitation, Physical Verification, Layout Closure, Advanced Process Nodes

Cadence Tools, FinFET process technologies, DRC LVS checking flows with Calibre