Analog Layout Engineer
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Position: Analog Layout Engineer
Location: Bangalore
Experience: 3 to 10 Years
Job Description:
Regards,
Karthik Kumar
[Confidential Information]
Job ID: 151487101
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout
Skills:
Routing, Device Placement, CMOS Process Technologies, Matching Techniques, Device Physics Fundamentals, Layout Strategies for Low-Noise and High-Precision Circuits, floorplanning, Layout Optimization, Signoff Methodologies
Skills:
reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso
Skills:
Calibre, Mixed Signal Layout, Physical Verification, Analog Layout, DRC, Custom Layout, virtuoso, LVS, Chip Level Integration, CAD Tools, Layout Electrical Parameters
Skills:
Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology
