Staff SoC Product & Test Engineer, AI Hardware

Position Description
The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla's machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

Tesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads. This role is located in Bengaluru, India. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.

Our Silicon Engineering team takes chips from first silicon through volume production — owning characterization, yield, diagnostics, and IP test. As a Staff SoC Product and Test Engineer, you will own the full arc from NPI bring-up and performance characterization through production yield optimization and IP-level test content, ensuring every product ships at validated quality and performance.

Responsibilities

Define characterization plans for processor cores and IPs — develop NPI performance stress tests across process, voltage, and temperature

Perform and correlate measurements across ATE and SLT platforms over volume — define guard bands and drive corrective actions for test platform alignment

Develop solutions to set optimal system voltage and frequency operating points — align from manufacturing screen through system operation

Own silicon bring-up — execute structural, functional, and parametric tests; debug failures and quantify performance shifts using accelerated stress

Analyze volume production data — identify and implement solutions to improve yield and throughput

Architect and deploy volume diagnostic data processing pipelines for SoC logic and memory

Integrate AI-based deep learning techniques to improve diagnostics convergence, fault isolation, and failure analysis success rates

Drive defect reduction with foundry partners — build defect paretos, recommend FA candidates, and validate improvements from process changes

Develop models to predict yield trends, detect anomalies, and drive corrective actions

Root cause qualification fails and field returns — develop new test content targeting identified fault types

Requirements

Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience

10+ years across SoC characterization, yield, diagnostics, and IP test engineering

Hands-on experience across ATE, SLT, and bench platforms

Deep expertise in PVT characterization, guard band definition, and ATE/SLT correlation

Experience with diagnostic data pipelines and AI/ML-based fault isolation techniques

IP test development experience for High-Speed IO and Mixed Signal IPs

Ability to use agentic AI flows to automate yield analysis, diagnostics, and test optimization