Own end-to-end physical implementation for major IP blocks and/or full-chip designs, ensuring alignment with ADI's Career Development Framework (Expertise, Autonomy & Scope, Business Impact).
Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis)
Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus).
Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.
Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability.
Automate design flows (e.g., hierarchical PNR, IO ring automation, Flash PG) to improve efficiency and quality; contribute to continuous flow enhancements.
Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones.
Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability.
Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement.
Demonstrate ADI values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results.
Required Qualifications:
Bachelor's or Master's in Electrical/Electronics Engineering or related discipline.
8+ years of hands-on experience of ASIC/SoC physical design at advance nodes such as 40,28,22,16 etc.
Strong proficiency in floorplanning, PNR, STA, and physical verification using industry EDA tools.
Experience developing or deploying automated flows (Tcl, Perl, Python) to improve design productivity.
Deep understanding of fabrication process limitations, ESD/IR/EM analysis, and robust sign-off methodologies.
Demonstrated ability to communicate clearly, collaborate cross-functionally, and work effectively in a fast-paced, innovative environment.
Preferred Qualifications:
Experience with hierarchical design and large-scale SoC integration.
Background in low power and multi-voltage design methodologies (UPF/CPF).
