Staff Engineer
- Posted a month ago
- Be among the first 10 applicants
Job Description
Looking for an experienced senior verification engineer with 8-10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
- Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM.
- Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB.
- Strong debugging skills to address TB issues quickly and test failures.
- Take responsibility for verification closure by addressing coverage and managing bug reports.
- Proficiency in using industry standard verification tools such as Questa, VCS or ModelSim.
- Experience with scripting languages like python, perl or TCL for automation tasks.
- Able to track & manage Daily and weekly progress and manage a team of 6 to 7 Engineers.
- Interact with the customer on the tasks and status updates.
More Info
About Company
Skills:
.NET, C#, Api Integration, Python, AWS Bedrock, LLM-based solutions, MCP servers, LLM orchestration, GEN AI Agentic AI
Skills:
.NET, C#, Nosql, Data Science, PLS, Python, Java, Ml, Sql, Pca, MLops, vector search, data pipelines, semantic retrieval, chemometrics, process control instrumentation, industrial analytics, secure LLM design, LLMs, Ai, Sensors, time-series data, process data acquisition, RAG, Process Automation
Skills:
Data Analytics, Deep Learning, Python, Machine Learning, LLM-based workflows, Document-processing pipelines
Skills:
Vcs, Tcl, Python, Perl, AHB, Questa, Uvm, AI-assisted engineering tools, AXI-Lite, systemverilog, Xcelium, APB, Axi, AMBA-based interconnect fabrics
Skills:
PowerShell, Python, SOTI MobiControl, HP Thin Clients, Enterprise MDM