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Unsupervised Layout Implementation: Independently execute layout designs across all hierarchies—from unit cells and blocks to complex MACRO, PHY, and full-CHIP levels—without supervision.
Autonomous Physical Verification: Own the complete verification flow (DRC, LVS, etc.). Ensure all results are double-checked, remaining errors are formally waived/confirmed, and comprehensive documentation is provided.
Architectural Mastery & Compliance: Maintain deep ownership of assigned architectures and Design Rule Manuals (DRM) across various process technologies (planar CMOS, FinFET, and advanced nodes).
BKM Optimization: Independently develop and implement test cases to achieve optimal technical solutions in the shortest timeframe while continuously improving Best-Known Methods (BKMs).
Project Improvement Planning: Proactively develop, implement, and innovate project improvement plans to ensure timely, cost-effective, and high-quality silicon output.
Operational Management: Manage and lead tasks, engineering groups, or projects. Drive the efficient implementation of task assessment, delegation, execution, review, and final submission.
Challenging the Status Quo: Actively evaluate and challenge existing workflows, documentation, and processes to guarantee long-term operational success.
Post-Mortem Integrity: Initiate and implement post-mortem reviews, ensuring all action items are closed out and robust technical/procedural countermeasures are developed.
Requirements:
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field, with a specialization in Integrated Circuit (IC) design.
5–8 years of relevant, hands-on experience in analog/mixed-signal or digital IC layout design and full-chip physical verification
Job ID: 149785205
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