Senior Engineer

Job Requirements

At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Role Overview

Drive full-chip or subsystem static timing analysis and timing closure across multiple modes and corners. The role needs strong constraint understanding, path-level debugging, timing-model awareness and the ability to translate analysis into implementable ECO actions.

Key Responsibilities

• Perform STA and timing signoff using PrimeTime and/or Tempus
• Validate SDC constraints, clocks, generated clocks, exceptions, IO delays and mode/corner coverage
• Analyse setup, hold, recovery/removal, clock-gating and other relevant timing checks
• Debug interface timing, block-to-block paths, clock interactions and constraint-quality issues
• Build, validate and use timing models for hierarchical analysis where applicable
• Analyse OCV/AOCV/POCV, SI/crosstalk and parasitic effects on timing convergence
• Generate timing ECO recommendations and work with PnR/implementation teams through closure
• Support LEC, extraction correlation, QoR reporting and signoff review readiness
• Collaborate with RTL, synthesis, PnR, DFT and methodology teams to resolve root causes
  
  

Required Skills & Expertise

• 5-10 years of relevant STA/timing closure experience at subsystem or full-chip level
• Strong hands-on expertise in PrimeTime and/or Tempus
• Strong SDC knowledge and experience debugging incorrect, incomplete or conflicting constraints
• Experience with MCMM timing analysis, path-based debugging and timing ECO generation
• Understanding of parasitic extraction using StarRC or equivalent
• Working knowledge of LEC using Formality or equivalent
• Exposure to implementation tools such as Innovus, ICC2 or Fusion Compiler for timing correlation
• Ability to communicate timing risks and closure actions clearly to implementation and design teams
  
  

Preferred Skills

• TCL scripting capability; Python is an advantage
• Familiarity with hierarchical timing models and interface closure
• Exposure to advanced-node timing effects without requiring proprietary programme details
  
  

Recruiter Knockout Questions

• Has the candidate owned STA closure at subsystem or full-chip level, not only generated timing reports
• Can the candidate explain how they validate SDC constraints and identify unconstrained or incorrectly constrained paths
• Have they debugged MCMM setup/hold issues and driven implementable ECO actions
• Which PrimeTime/Tempus analyses were used hands-on, including SI and variation methodology where applicable
• Have they worked with PnR and RTL teams until timing signoff convergence
  
  

Education

BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.