Senior Engineer, ASIC Design

Position Overview:

In this role, you will be the cornerstone of our hardware team, defining the micro-architecture and executingthe RTL implementation for our next-gen AI engines. You will tackle the industry's toughest challenges: balancing massive throughput with ultra-low latency. You will lead the design of complex datapaths, integrate RISC-Vsubsystems, and push the limits of PPA to deliver world-class silicon.

Responsibilities:

• Architectural Leadership: Translate high-level AI algorithms into robust micro-architecture specifications for high-performance compute engines.
• Core Design: Own the RTL implementation of critical modules, focusing on low-latency and high-throughput datapath optimization.
• Advanced Compute Units: Design and optimize high-efficiency ALU and specialized arithmetic units tailored for AI workloads.
• PPA Mastery: Drive the design through synthesis and timing closure, ensuring the silicon meets aggressive power and area targets.
• Technical Mentorship: Work closely with architecture and software teams to define the hardware-software interface and mentor junior engineers.

Qualifications / Requirements:

• Education: BS/MS/PhD in EE, CS, or related field with minimum 3+ years of deep experience in ASIC Design and successful tape-outs.
• Mastery of SystemVerilog/Verilog and a proven track record of designing complex, high-frequency digital logic.
• Extensive experience in Datapath optimization, including pipeline balancing and advanced handshaking protocols.
• Expert knowledge of high-performance bus protocols and interconnect architectures. Proficiency in scripting (Python, Perl, or C/C++) for automation and modeling.

Preferred Skills:

• GPU/ALU Pedigree: Prior experience in designing GPU shaders, execution units (EUs), or high-performance ALUs. we value your expertise in complex arithmetic pipelines.
• RISC-V Expertise: Deep familiarity with RISC-V cores, custom instruction extensions, or vector processors.
• Leadership DNA: Proven experience as a Technical Lead, with the ability to build and inspire high-performing engineering teams.