Senior Design Verification Engineer
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Position
・ Senior Engineer
Experience and knowledge
・Large scale RTL design over 100k gate in Verilog HDL and VHDL, including architecture investigation, logic design, logic verification, timing optimization for the critical path
・Extracting the verification items from the specification
・Creating the testbench and verifying on the bench
Educational background
・ Bachelor's degree in computer engineering, electronics, electronics and communications engineering, computer science or similar course
Language
・ English
Working days and hours
Monday to Friday, 8am to 5pm
Work location
・ Philippines
Job ID: 152736285
