Collaborate with hardware architects, design engineers, IP providers, software developers, and platform validators to deliver high quality verification output
Verify designs at block-level, sub-system level, and/or full chip SoC level
Develop comprehensive verification plans and strategies with clear and measurable metrics
Derive test items and coverage goals from design and architecture documents
Architect, implement, and maintain verification environments and components of various complexity
Implement directed and constrained random test cases
Debug and analyze complex digital designs
Analyze test results and create detailed bug reports
Create project schedule, measure progress, create detailed reports, and drive a project to completion
Develop best practices and help improve design verification workflow
Preferred Expertise
Experienced in developing test plans and identifying test items
Fluent in Verilog and SystemVerilog
Experienced in Universal Verification Methodology (UVM)
Experienced with scripting languages (Shell, TCL, Perl, Python, etc.)
Experienced in developing UVM environments and components from scratch
Experienced in using third-party Verification IP (VIP)
Experienced in industry protocols and standards (AXI, AHB, APB, CHI, PCIe, USB, NVMe, DDR, Ethernet, etc.)
Experienced in Linux operating system
Knowledgeable in SystemVerilog Assertions (SVA) and Formal Verification
Demonstrated success in executing entire digital verification process
