Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Senior Design Verification Engineer
- Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.
- Should be an enthusiastic and a quick learner of the verification flow.
Job Description:
- SV / UVM Test bench development and test cases coding
- Code and Functional coverage analysis and closure
- Work with team for verification closure
- Experience with python or any other scripting language is a plus
- Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.
Experience: 4 to 6 Years
Location: Hyderabad
More Info
Job Type:
Industry:
Function:
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Key Skills
SV
IJTAG protocol
Functional coverage analysis
Test bench development
Test cases coding
About Company
Skills:
Debugging Expertise, SoC Verification, Uvm, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Hardware-Software Integration, Coverage-Driven Verification
Skills:
Vcs, System Verilog, Xcelium, Verdi, DVE, Questa, Uvm, SVA assertions
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
Skills:
simvision , python, perl, SV-UVM, Verdi, Verisium, Xcellium, Digital Simulation Tools, virtuoso