Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft Labs7-9 Years
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 10+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
- Hands-on experience in SoC-level and IP-level verification, including VIP integration, coverage-driven verification, and debugging
- Strong proficiency in SystemVerilog/UVM testbench architecture, including assertions, scoreboarding, and functional coverage
- Experience in IP and sub-system verification, including test plan creation, execution, and review
- Solid understanding of verification methodologies, regression management, and debug flows
- Proficiency in scripting languages such as Python or Perl for automation and regression support
- Ability to collaborate effectively with design, architecture, and cross-functional teams
- Strong analytical, problem-solving, and communication skills
More Info
Job Type:
Industry:
Function:
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Key Skills
VIP integration
testbench architecture
verification methodologies
scoreboarding
coverage-driven verification
execution and review
assertions
regression management
debug flows
functional coverage
About Company
Skills:
Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA
Skills:
Perl, Verilog, Python, Uvm, SVA, systemverilog
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers