Digital Design Engineer

The Group

The Joint Development Team (JDT) is a small, independent, cross-disciplinary group whose charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas and to collaborate with focused product development teams to get these advances to the marketplace. Current and future research areas include advanced medical devices, energy metering and fault detection, high-speed imaging, security electronics, ultra-precision references and data converters.

The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision, and of broad industrial experience. The group culture aims to foster a challenging, exciting, and supportive environment.

The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment and will be exposed to various groups across the corporation's many sites through all stages of the development cycle.

The Role

The P4 Digital Design + DV Engineer will lead digital RTL design while also driving full-flow verification activities (UVM, testbench architecture, coverage closure). The engineer will collaborate with analog/mixed-signal designers and may switch between design and DV roles depending on project needs.

Essential Duties and Responsibilities:

Digital Architecture & RTL Design

• Define RTL architecture, module boundaries, interfaces, and control logic.
• Develop and debug synthesizable SystemVerilog/VHDL RTL that meets functional, timing, and power requirements.
• Architect and implement state machines, datapaths, arithmetic units, protocol engines, and digital control loops.
• Perform design checks (lint, CDC, reset‑domain crossing, DFT readiness) and support synthesis/STA closure.

Integration & Cross Functional Collaboration

• Lead or contribute to system or chip-level architecture planning
• Support mixed-signal simulations, co-simulation flows, and integration testplans.
• Collaborate with DV engineers to ensure correct verification scope, coverage, and feature signoff.
• Lead or aid in the development of a verification strategy, verification plan, and test strategy.
• Support the development of a UVM based testbench and the overall verification effort
• Identify and implement constrained random and directed tests for verification
• Contribute to and support the overall verification efforts

Ownership & Technical Leadership

• Lead design reviews, documentation, and technical mentoring of junior digital designers (P1–P3).
• Evaluate, propose, and introduce improvements to digital design methodologies and flows.

Minimum Qualifications:

• BS/MS in ECE, EE, CpE, or related field.
• 5–10 years experience in digital RTL design and subsystem ownership.
• Strong SystemVerilog/Verilog coding and debugging skills.
• Experience with CDC, lint, DFT, synthesis, and timing analysis.
• Strong scripting ability (Python/Perl/TCL).
• Excellent communication and cross‑team collaboration skills.