Design Verification Engineer
Design Verification Engineer
HCL TechBee7-10 Years
- Posted 8 days ago
- Be among the first 10 applicants
Job Description
Looking for a Design Verification Engineer with 7-10 years of ASIC/SoC verification experience, strong expertise in UVM, Formal Verification, SystemVerilog/Verilog, verification environment development, debugging, and scripting (Python/Perl)
Mandatory Skills
- 7 to 10 years of experience in Design Verification (DV) for ASIC/SoC
- Strong hands-on experience in UVM (Universal Verification Methodology)
- Experience in Formal Verification
- Strong knowledge of Verilog/SystemVerilog or VHDL
- Experience in developing and debugging complex testbenches and verification environments
- Strong understanding of RTL design concepts
- Experience with simulation tools such as: Synopsys VCS,Cadence Incisive/Xcelium,ModelSim,
- Scripting experience in Python or Perl
- Strong debugging and root cause analysis skills
Preferred Skills
- Experience with formal verification tools
- Team leadership or mentoring experience
- ASIC/SoC verification at block and subsystem level
- Code reviews and verification methodology improvements
More Info
Key Skills
Cadence Incisive
Xcelium
complex testbenches
Synopsys VCS
RTL design concepts
verification environments
About Company
Skills:
code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi
Early Applicant
Skills:
Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
Skills:
Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog