ASIC Engineer Design
- Posted a month ago
- Over 50 applicants have applied
Job Description
ASIC Engineer Design Responsibilities
- Architecture exploration
- Micro-architecture development
- RTL development using Verilog, System Verilog and HLS
- Lint, CDC, Synthesis, Power Optimization
- Soft and hard IP identification, selection and integration
- Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with implementation team to close the design on timing and power
Minimum Qualifications
- At least 7+ years of silicon development experience
- Track record of first-pass success in ASIC Development
- Experience with Verilog or System Verilog
- Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs, OR Experience in SoC Micro-architecture, Design and Integration, OR Implementation, Power methodology development
- Experience working across multiple projects
- Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Preferred Qualifications
- Experience in data path development
- Experience in CPU, NOC, Memory and Peripheral Subsystems
- Experience in HLS
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- Experience with Power Analysis and Optimization
- Experience with scripting languages (TCL, Python, Perl, Shell-scripting)
More Info
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Key Skills
ASIC Engineer Design
Architecture exploration
Micro-architecture development
About Company
Skills:
power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis
Skills:
ASIC development cycle, ASIC design methodologies, develop solutions, cross-functional teams, Rtl Design, architecture, Verification
Skills:
Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor
Skills:
bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB
Skills:
spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging