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Job ID: 150873229
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, PEX and post-layout simulation correlation, matching shielding guard rings isolation and parasitic optimization, Calibre PVS, advanced-node analog custom layout
Skills:
Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction
Skills:
reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso
Skills:
Calibre, Mixed Signal Layout, Physical Verification, Analog Layout, DRC, Custom Layout, virtuoso, LVS, Chip Level Integration, CAD Tools, Layout Electrical Parameters
Skills:
Cadence Virtuoso, Synopsys IC Compiler, Parasitic Extraction, TSMC 3nm and 5nm, analog layout design