SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog

C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog

Scripting Language, Python, SV, IJTAG protocol, Functional coverage analysis, Test bench development, Test cases coding, Uvm

Unix, Shell, Pcie, Linux, System Verilog, Python, VIP coding, Constraint based Random verification, Coverage strategies and measurement, Skill, Test cases coding, Cadence, Mentor, Uvm, Digital Design and Verification methodologies, DDR verification, Synopsys simulation suites, EDA Tools, Verilator, Test Plan design

Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Vcs, System Verilog, Xcelium, Verdi, DVE, Questa, Uvm, SVA assertions