Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc

Verilog, Synthesis, ECO fixes, asynchronous interfaces, Timing Concepts, formal verification, SoC design and integration, multi-clock designs, SoC clocking reset architecture, System-Verilog, Logic design RTL coding