Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction

Cadence Virtuoso, Synopsys IC Compiler, Parasitic Extraction, TSMC 3nm and 5nm, analog layout design

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

shielding , ESD latch-up prevention, Analog Custom Layout Design, Guard rings, TI Texas Instruments project environment, Cadence Virtuoso, Matching symmetry, Layout verification tools, Common centroid, Advanced process nodes foundry rules, DRC LVS ERC EM IR checks

matching , shielding , Dac, Routing, GXL, Cadence Virtuoso Layout XL, LVS, Bandgap, PEX, EMIR verification, floorplanning, ADC, advanced technology nodes, Op-Amp, LDO, ERC, Placement, DRC, Analog Mixed-Signal Layout Design, SERDES, Pll

Electron migration, Analog layout design, Voltage drop, Process design rules, Signal planning, Micro-floor planning, High speed SerDes layouts, IR ESD, TSMC N3 technology, Design verification tools

Vdc, custom analog layout design, EDA Tools, Antenna, ADC, Circuit Design, RV high voltage flows, noise fixes, LDO, layout validation, Charge pump, density, DRCs, scripting skills, Vlsi Design, Virtuoso XL