automation, Ovm, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, Specman, SDF sim debug, test-bench development, HVL, closure constraint randomization, functional and code coverages, assertions development, eRM methodology, formal verification

Ovm, automation, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification