SystemVerilog Assertions (SVA), Specman E, Uvm, systemverilog

Gate Level Simulations, subsystem SoC verification, real number modeling, regression management, Vplan execution, Uvm, systemverilog

Unix, Shell, Pcie, Linux, System Verilog, Python, VIP coding, Constraint based Random verification, Coverage strategies and measurement, Skill, Test cases coding, Cadence, Mentor, Uvm, Digital Design and Verification methodologies, DDR verification, Synopsys simulation suites, EDA Tools, Verilator, Test Plan design

Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools

Debugging Expertise, SoC Verification, Uvm, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Hardware-Software Integration, Coverage-Driven Verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Vcs, System Verilog, Xcelium, Verdi, DVE, Questa, Uvm, SVA assertions