Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, UVM methodology, Coverage-driven verification, systemverilog, Functional Verification