Verilog, Ethernet, System Verilog, coverage closure techniques, Flex Ethernet, Otn, Uvm, regression management flows, formal verification, assertion-based test, self-checking testbenches, Interlaken

Perl, Vcs, System Verilog, Python, Tcl, Questa, Modelsim, Uvm

code coverage , SoC Verification, MCU Verification, Uvm, Functional Coverage, Assertion Coverage

Coverage models, Uvm, CPU Core Verification, Constrained-random tests, systemverilog, Architecture Validation, Testbenches, Checkers, Scoreboards

Cadence - Virtuoso, Perl, Python, Tcl, Mentor tools, SV, Verilog Hdl, Cadence, Uvm, Spice Simulator, Verilog-AMS, AMS simulation environment, Verilog-D, Synopsys, Verilog-A

Tcl, Python, Perl, SV, SoC Verification, Uvm, Functional vectors generation, MBIST verification, SV UVM monitors, Test controller architecture, ATE Functional CHAZ vector enablement

lattice , Ddr3, C, Usb, Verilog, System Verilog, Ethernet, Pcie, AHB, RTL synthesis concepts, ARM Cortex platforms, SystemC-DPI testing methodologies, embedded processors, processor architectures, Veloce platforms, DSP theory, AMBA, UVM-acceleration, SERDES, Microsemi, Xilinx, VirtuaLAB environments, Altera, APB

Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools