static timing analysis, PCIe protocol stack, MSI interrupt handling, Simulation Tools, CDC design principles, systemverilog, asynchronous FIFO implementation, RTL design using Verilog, DMA engines, PXC interfaces, Synthesis, linting, formal verification, waveform debugging, assertion-based design methodologies

Ovm, automation, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, SDF sim debug, Specman, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification