Designer, Layout

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.
SUMMARY:
The IC Layout Designer is mainly responsible for the creation of top-level layouts. He/she will mostly work with schematic designers, block layout resources, section leads, project managers, and assembly engineers. His/her job is to meet schedule, design, and quality requirements set by project stakeholders. As top layout lead, he is responsible for managing deliverables of layout resources, doing the actual tape-out process to the foundry, and creating bonding diagrams for the chosen target package/s. He/she will have the opportunity to mentor new hires or interns and may likewise be tapped to be a part of other development initiatives for the layout team.
KEY QUALIFICATIONS:

• Extensive Top/Chip level layout experience
• Familiarity with various Tapeout procedures
• Familiarity with package selection procedures and design checks
• Strong fundamental knowledge in semiconductor device physics, cross-section, and construction
• Strong fundamental knowledge of layout principles, IC reliability, and failure mechanisms
• Proficiency in Cadence Virtuoso XL and Calibre verification tools is an advantage

• BS Electronics or Electrical Engineering
• At least 6 years of relevant working experience

• Strong communications skills, both oral and written
• Able to work and effectively collaborate with a cross-functional and global team
• Strong leadership skills
• Layout experience in any of the following areas is an advantage: ADC, DAC, High-voltage applications
• Layout experience in the following technology nodes is a plus: 0.18um, 40nm