static timing analysis, Automation Frameworks, Verilog, low-power implementation methodologies, design constraints, generative AI tools, functional validation, AI-assisted engineering technologies, systemverilog, Rtl Design, Logic Synthesis, EDA Tools, Timing Closure

PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Verification Components (UVCs), Assertions (SVA), Uvm, systemverilog, Functional Coverage, Debug Techniques