Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Memory Management, virtualization, System Verilog, Python, Perl, HW-SW debug, Uvm, power management fundamentals, Functional Coverage, DV test bench, Virtual Memory concepts, Scoreboards, Post-Silicon bring-up, coherency protocols, IP Sub System design verification, Assertion, Checkers, Trackers

.NET, .Net Core, C#, Graphql, Kafka, Css3, Angular, Automated Testing, Git, Typescript, Javascript, Gcp, Docker, Html5, ASP.NET, Distributed Systems, Azure, Kubernetes, AWS, NoSQL databases, Microservices architecture, CI/CD pipelines, Service Bus

Apis, Node.js, Microservices, Angular, Testing Frameworks, Typescript, Javascript, System Design, CI CD, service-oriented architecture, Object-Oriented Design, observability

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques

Java, Scala, Distributed Systems, Python, Go, Backend Systems Infrastructure