Version Control Systems, Soc Architecture, Asic Design Verification, BFMs, UVCs, Regression automation, Functional and code coverage methodologies, Uvm, SoC IP verification environments, systemverilog, VIPs

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

C, C++, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, Asic Design Verification, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment