Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification

Perl, Verilog, Python, Tcl, Physical Design, Signoff, VHDL, Full-chip aspects, IP integration, Timing Verification

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL