Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Java, Kafka, Python, API design, Incident Management, Gcp, Distributed Systems, Kubernetes, Testing, Go, Alerting systems, Flink, Microservices architecture, developer tools, Streaming Data, SDKs, Monitoring

Memory Management, virtualization, System Verilog, Python, Perl, HW-SW debug, Uvm, power management fundamentals, Functional Coverage, DV test bench, Virtual Memory concepts, Scoreboards, Post-Silicon bring-up, coherency protocols, IP Sub System design verification, Assertion, Checkers, Trackers

Python, MATLAB, Silicon Validation, characterization, VNAs, BERTs, High-speed lab equipment, Oscilloscopes, ATE platforms, Signal integrity measurement, Spectrum analyzers

display technologies , Python Programming, Functionality, Bit Depth Color, OS Ecosystems, Bitstream Verification, MIPI DSI-2, Introspect SV series systems, FPGA platforms, Scaling Processing, PVT Testing, Frame Buffer, Lab Instrumentation, Pixel Formats, SV UVM, Low-Level Software, Continuous Integration tools

Encryption, Negative Testing, Verilog, Soc, Python, configuration robustness, FPGA security, fault injection, secure boot, key management