Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

flows and methodologies, Asic Physical Design, collaboration and teamwork, EDA vendor relationships

Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification

Automation Frameworks, Perl, Python, Tcl, AI-native automated methodologies, Methodology, Physical Design, Sub-3nm device physics

Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification

Perl, Verilog, Python, Tcl, Physical Design, Signoff, VHDL, Full-chip aspects, IP integration, Timing Verification