static timing analysis, low-power design methodologies, LINT, Cadence Tools, cdc, Logic Synthesis, Rtl Design, scan testability, DFT sign-off, physical design interactions, formal verification, ASIC EDA tools, Verification, Dft

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

data engineering , Docker, Kubernetes, Python, AWS, AI Engineering

quantitative analytics , Vba, Excel, Python, C#, C++, R, VaR, Market Risk Model Development, risk modelling, stochastic calculus, stochastic processes, Derivatives, Derivatives Pricing, probability theory, Quantitative Modelling Techniques, Time-series Analysis