Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

C, System Verilog, AXI-AMBA protocol variants, Uvm

Test Planning, C, Systemc, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, formal verification, constrained-random verification, power-aware verification

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Perl, Ruby, System Verilog, make, Uvm, Asic verification, Rtl Design, formal verification, TestBench Development