Perl, Python, Tcl, UPF, power simulation on VCS, UVM Test Bench development

Excel, Python, Ms Word

Perl, Python, Tcl, FineSim, Hspice, CTS, POCV concepts, primetime, Monte Carlo analysis, STA tools, cross-talk, STA fundamentals, ICC2, Tempus, Spice simulations, Signal Integrity, Innovus, Timing Constraints, Parasitic Extraction, noise, ASIC back-end flows, AOCV

Liberty .lib, Python, Tcl, pulse-width verification, OCV, setup hold analysis, ETM timing model generation, ONFI PHY, Cadence Tempus, DDR PHY, Innovus, MMMC timing analysis, Cadence digital implementation and signoff flow, IO Expander, POCV methodologies, Genus, AI ML-enabled EDA methodologies, recovery removal checks, SDF generation, AOCV

synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff

Computer Engineering, Tcl, low-power designs, Computer Science, Electrical Engineering, coding constraints

synopsys primetime , Perl scripting, Static Timing Analysis, SDC constraints, RTL Synthesis, STA timing constraints, mmc, Timing optimization, Critical path analysis, ASIC SoC implementation and signoff methodologies, Setup hold analysis, Timing Closure, MCMM, Synopsys Design Compiler, ECOs and timing fixes

synopsys primetime , Perl, Shell scripting, Python, Tcl