Principal Engineer – Physical Design

Location: Bengaluru

Experience: 12–18 Years

Role Overview

We are looking for a Principal Physical Design Engineer with deep expertise in full-chip implementation and sign-off for complex ASIC/SoC designs. The role requires strong hands-on experience with Cadence Innovus, STA and EM/IR analysis.

Key Responsibilities

Lead full-chip Physical Design from netlist through tape-out.
Drive floorplanning, power planning, placement, CTS, routing and physical optimization.
Strong hands-on expertise in Cadence Innovus for implementation and PPA optimization.
Own timing closure and Static Timing Analysis (STA) across MMMC scenarios.
Analyze and resolve setup/hold, congestion, DRC and timing violations.
Drive EM/IR analysis and power integrity closure using industry-standard sign-off tools.
Collaborate with RTL, Synthesis, STA, DFT and Sign-off teams to resolve complex implementation issues.
Drive ECO implementation, timing optimization and sign-off closure.
Support advanced-node full-chip designs and tape-out activities.
Provide technical leadership and mentor senior Physical Design engineers.

Required Expertise

12–18 years of hands-on ASIC/SoC Physical Design experience.
Proven full-chip implementation experience.
Strong expertise in Cadence Innovus.
Strong knowledge of STA, timing closure, MMMC and sign-off methodologies.
Hands-on experience with EM/IR analysis and power integrity.
Good understanding of physical verification, DRC/LVS and advanced-node challenges.
Experience with Tempus/PrimeTime, Voltus or equivalent sign-off tools.
Strong scripting skills in Tcl/Python/Perl.
Excellent technical problem-solving and cross-functional collaboration skills.

Principal Engineer Physical Design