Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

DDR, Pcie, Perl, Vcs, Python, Tcl, Uvm, Axi, Verdi, APB, Questa, systemverilog