Synopsys tool suite, Synthesis and STA, IR EM analysis and resolution, physical design verification, ICV or Calibre tools, scripting languages like Tcl and Python, block level and full-chip physical verification methodology, block physical design PDV and IR, full chip floor-planning and integration, complete physical design flow, block subsystem timing closure

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, device physics, Low power design implementation

Routing, RTL synthesis, Placement, Floor Planning

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Synthesis and Signoff flows, IR Drop and EM analysis

Physical Design, Deep sub-micron technology, Timing Closure, Power Planning, Floor Planning, Signal integrity analysis, Place And Route