Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Github, virtualization, OpenStack, Dns, Firewalls, routing, DHCP, Gcp, Terraform, shell scripting, Ansible, Pure Storage, Azure, Python, Kubernetes, AWS, networking fundamentals, Linux systems administration, Dell PowerStore, Infrastructure-as-Code

Perl, Python, Tcl, FineSim, Hspice, CTS, POCV concepts, primetime, Monte Carlo analysis, STA tools, cross-talk, STA fundamentals, ICC2, Tempus, Spice simulations, Signal Integrity, Innovus, Timing Constraints, Parasitic Extraction, noise, ASIC back-end flows, AOCV

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

platform management , C, Automation Frameworks, Shell scripting, Python, Embedded Linux, Linux, Debugging, Firmware Development, Embedded Software Development, Boot flows, Firmware initialization, Security, Embedded Systems, power management, Firmware architecture, Customer Engineering, Applications Engineering, Platform Engineering