occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis

Non-volatile Memory (Flash, Dft, MRAM, MBIST, ReRAM, Synopsys, iJTAG IEEE 1687, SoC MCU Architecture, TestMAX, Functional Safety, power management, JTAG IEEE 1149.1, ATPG, Scan Compression, Mentor, Tessent, Audio, Rf, Mixed-signal Design, LBIST, Ate, Digital Design Flows

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Logic Design, On-chip scan compression, Scan BIST, Fault Simulation, ATPG