Nvme, SAS, Silicon Validation, Pcie, Verilog, physical implementation, Synthesis, functional safety, Architecture Design, verification methodologies, Reliability, advanced verification techniques, Uvm, tape-out, silicon security, systemverilog, Rtl Design, Dft, Timing Closure, performance optimization, CXL, power management, Design Methodologies

Veeva, Sas Programming, Forms Design, Gcp, Database Management, EMA, edit check programming, risk management, Medidata Rave, Stakeholder Management, Data Review, Operational Management, Clinical Data Programming, Fda, Leadership, global regulatory requirements, Full-Service delivery models, ICH Guidelines, portfolio governance, EDC build lifecycle

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

biostatistics , cdms , Ml, Hl7, SAS, Python, Sycamore, Medidata Rave, Domino, Ai, GenAI, ctms, epro, Oracle InForm, EDC Platforms, USDM, SAS Viya, statistical programming, LSAF, Clinical Data Management, Nurocor, FHIR, R, Clinical Data Standards, Formedix, eClinical Elluminate, eTMF, Oracle LSH, Veeva EDC

Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis