Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC

Bonding System, CYMCAP, HV cable design, Earth Continuity, Project management, Installation testing and maintenance, Co-Axial Cable, Short circuit calculations, Cable sizing and insulation specifications, Report Preparation, Technical problem-solving, Site surveys and assessments, Compliance with standards and regulations, Quality control checks, Cable Modelling Software, Health Safety compliance, Cable Bonding layout

power delivery , automation, Firmware, Test Plans, Logic Design, multi-unit fleet testing, manufacturing, silicon design, PVT stress, thermal dependencies, platform programs, platform engineering, cross-functional alignment, NVIDIA GPU SoC, System Validation, system-stress campaigns, Signal Integrity, Software, firmware and software interaction, Dft, AI-enabled debug, Debug, validation workflows

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

power delivery , Test Plans, Firmware, automation, Logic Design, AI-enabled debug, thermal dependencies, Debug, system-stress campaigns, multi-unit fleet testing, software interaction, System Validation, platform programs, cross-functional alignment, Signal Integrity, PVT stress, NVIDIA GPU SoC, validation workflows

Non-volatile Memory (Flash, Dft, MRAM, MBIST, ReRAM, Synopsys, iJTAG IEEE 1687, SoC MCU Architecture, TestMAX, Functional Safety, power management, JTAG IEEE 1149.1, ATPG, Scan Compression, Mentor, Tessent, Audio, Rf, Mixed-signal Design, LBIST, Ate, Digital Design Flows