Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

power management, Analog Design, data converters, ESD latch-up, analog feedback loops, Layout, references, control-loop stability, signal-conditioning blocks, charge pumps, Sensors, mixed-signal IC development, Verification, protection circuits, LDOs, switching converters, Simulation, IC-level reliability

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, Uvm, systemverilog, Scoreboarding, Performance bottleneck analysis, Simulation-based verification, IP-level verification, coverage analysis, Regression, Performance verification, Functional coverage, Assertions, Constrained-random verification, Testbench architecture, Coverage closure, SVA, formal verification, Reference models

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

Bsp, Networking, middleware, functional safety, memory subsystems, camera technologies, high-speed interfaces, system architecture reviews, debug methodologies, SoC architectures, Signal Integrity, platform integration, power management, embedded software interactions, Hardware Design