Perl, Python, ASICs, Analog behavioral models, System Verilog Programming, Chipsets, Digital Verification

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

code coverage , System Verilog, IC verification tools, DIMM, assertions, DDR5, DDR4, Uvm, functional coverage, cover groups, LPDDR5